1. Field of the Invention
The present invention relates to a magnetic thin-film memory device, particularly to a random access memory provided with a memory cell having a magnetic tunneling junction (MTJ).
2. Description of the Background Art
An MRAM (Magnetic Random Access Memory) device is watched as a memory device capable of storing data in a nonvolatile manner at a low power consumption. The MRAM device is a memory device for storing data in a nonvolatile manner by using a plurality of magnetic thin films formed on a semiconductor integrated circuit and capable of random-accessing each magnetic thin film.
Particularly, it is recently announced that performances of an MRAM device is remarkably advanced by using a magnetic thin film utilizing a magnetic tunnel junction (MTJ) as a memory cell. An MRAM device provided with a memory cell having a magnetic tunnel junction is disclosed in technical documents, such as “A ions Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC Digest of Technical Papers, TA7.2, February 2000 and “Nonvolatile RAM based on Magnetic Tunnel Junction Elements”, ISSCC Digest of Technical Papers, TA7.3, February 2000.
FIG. 42 is a schematic diagram showing a configuration of a memory cell having a magnetic tunnel junction (hereafter also merely referred to as MTJ memory cell).
Referring to FIG. 42, an MTJ memory cell is provided with a magnetic tunnel junction portion MTJ whose resistance values are changed in accordance with the level of storage data and an access transistor ATR. The access transistor ATR is constituted of a field-effect transistor and connected between the magnetic tunnel junction portion MTJ and a ground voltage Vss.
A write word line WWL for designating data write, a read word line RWL for designating data read, and a bit line BL serving as a data line for transferring an electrical signal corresponding to the level of storage data under data read and data write are arranged on an MTJ memory cell.
FIG. 43 is a conceptual diagram for explaining the operation for reading data from an MTJ memory.
Referring to FIG. 43, a magnetic tunnel junction portion MTJ has a magnetic layer having a constant-directional fixed magnetic field (hereafter also simply referred to as a fixed magnetic layer) FL and a magnetic layer having a free magnetic field (hereafter also simply referred to as a free magnetic layer) VL. A tunnel barrier TB constituted of an insulating film is set between the fixed magnetic layer FL and the free magnetic layer VL. A magnetic field having a direction same as or different from the direction of the fixed magnetic layer FL is written in the free magnetic layer VL in a nonvolatile manner in accordance with the level of storage data.
Under data read, the access transistor ATR is turned on in accordance with activation of the read word line RWL. Thereby, a sense current Is supplied from a not-illustrated control circuit is circulated as a constant current through a current path from the bit line BL to the magnetic tunnel junction portion MTJ, access transistor ATR, and ground voltage Vss.
Resistance values of the magnetic tunnel junction portion MTJ are changed in accordance with the magnetic-field-directional relative relation between the fixed magnetic layer FL and the free magnetic layer VL. Specifically, when the magnetic-field direction of the fixed magnetic layer FL is the same as a magnetic-field direction written in the free magnetic layer VL, the resistance value of the magnetic tunnel junction portion MTJ decreases compared to the case in which the both magnetic-field directions are different from each other.
Therefore, under data read, a voltage drop caused at the magnetic tunnel junction portion MTJ by the sense current Is differs in accordance with a magnetic direction stored in the free magnetic layer VL. Thereby, by starting the supply of the sense current Is after once precharging the bit line BL to a high voltage, it is possible to read the level of the data stored in an MTJ memory cell by monitoring a change of voltage levels of the bit line BL.
FIG. 44 is a conceptual diagram for explaining the operation for writing data in an MTJ memory cell.
Referring to FIG. 44, under data write, a read word line RWL is inactivated and an access transistor ATR is turned off. Under the above state, a data write current for writing a magnetic field in a free magnetic layer VL is supplied to a write word line WWL and a bit line BL. The magnetic-field direction of the free magnetic layer VL is decided by a combination of directions of data write currents flowing through the write word line WWL and bit line BL.
FIG. 45 is a conceptual diagram for explaining the relation between directions of a data write current and a magnetic field under data write.
Referring to FIG. 45, a magnetic field Hx shown by a horizontal axis shows the direction of a magnetic field H (WWL) generated by a data write current flowing through a write word line WWL. A magnetic field Hy shown by a vertical axis shows the direction of a magnetic field H (BL) generated by a data write current flowing through a bit line BL.
A magnetic-field direction stored in a free magnetic layer VL is newly written only when the sum of the magnetic fields H (WWL) and H (BL) reaches the region outside of the asteroid curve shown in FIG. 25. That is, when a magnetic field corresponding to the region inside of the asteroid curve is applied, a magnetic-field direction to be stored in the free magnetic layer VL is not updated.
Therefore, to update the data stored in a magnetic tunnel junction portion MTJ through the write operation, it is necessary to supply current to both the write word line WWL and bit line BL. A magnetic-field direction once stored in the magnetic tunnel junction portion MTJ, that is, storage data is held in a nonvolatile manner until new data is written.
Also under the data read operation, the sense current Is flows through the bit line BL. However, because the sense current Is is set so as to be smaller than the above data write current by 1 digit or 2 digits, the data stored in an MTJ memory cell is not easily erroneously rewritten due to the sense current is under data read.
The above technical documents disclose an art for integrating the above MTJ memory cell on a semiconductor substrate to constitute an MRAM device serving as a random access memory.
FIG. 46 is a conceptual diagram showing MTJ memory cells integrated and arranged in a matrix.
Referring to FIG. 46, it is possible to realize a highly-integrated MRAM device by arranging the MTJ memory cells on a semiconductor substrate as a row. FIG. 46 shows a case in which the MTJ memory cells are arranged in n rows×m columns (n, m: natural number).
As already described, it is necessary to arrange bit line BL, write word line WWL, and read word line RWL on each MTJ memory cell. Therefore, it is necessary to arrange n write word lines WWL1 to WWLn, n read word lines RWL1 to RWLn, and m bit lines BL1 to BLn on n×m MTJ memory cells arranged in a matrix.
Thus, it is general to set an independent word line to an MTJ memory cell correspondingly to the read operation and write operation respectively.
FIG. 47 is a structural drawing of an MTJ memory cell formed on a semiconductor substrate.
Referring to FIG. 47, an access transistor ATR is constituted in a p-type region PAR on a semiconductor substrate SUB. The access transistor ATR has source/drain regions 110 and 120 and a gate 130. The source/drain region 110 is connected with a ground voltage Vss through a metallic wiring formed on a first metallic-wiring layer M1. A metallic wiring formed on a second metallic-wiring layer M2 is used for a write word line WWL. Moreover, a bit line BL is provided for a third metallic-wiring layer M3.
A magnetic tunnel junction portion MTJ is set between the second metallic-wiring layer M2 on which a write word line WWL will be formed and the third metallic-wiring layer M3 on which a bit line BL will be formed. The source/drain region 120 of the access transistor ATR is electrically connected with the magnetic tunnel junction portion MTJ through a metallic film 150 formed on a contact hole, the first and second metallic-wiring layers M1 and M2, and a barrier metal 140. The barrier metal 140 serves as a cushion set to electrically connect a magnetic tunnel junction portion MTJ with a metallic wiring.
As already described, in the case of an MTJ memory cell, a read word line RWL is formed as a wiring independent of a write word line WWL. Moreover, it is necessary to supply a data write current for generating a magnetic field having an intensity equal to or larger than a predetermined value under data write to the write word line WWL and bit line BL.
On the other hand, the read word line RWL is formed to control the gate voltage of the access transistor ATR but it is unnecessary to positively supply current to the line RWL. Therefore, to improve an integration degree, a read word line RWL has been constituted of a polysilicon layer or polycide structure on the same wiring layer as the gate 130 without newly forming an independent metallic wiring layer.
By using the above configuration, it is possible to control the number of metallic wiring layers and integrate and arrange MTJ cells on a semiconductor substrate. However, because a read word line RWL is constituted of a polysilicon layer or the like, it has a comparatively large resistance value. Thereby, problems occur that a signal propagation delay increases in the read word line RWL under data read and acceleration of data read operation is impeded.
Moreover, a configuration is known which uses a PN-junction diode as an access device instead of an access transistor as the structure of an MTJ memory cell which can be further integrated compared with the MTJ memory cell shown in FIG. 42.
FIG. 48 is a schematic illustration showing the configuration of an MTJ memory cell using a diode. Referring to FIG. 48, the MTJ memory cell MCDD using the diode is provided with a magnetic tunnel junction portion MTJ and an access diode DM. The access diode DM is connected between the magnetic tunnel junction portion MTJ and a word line WL by assuming the direction from the junction MTJ toward the word line WL as the forward direction. A bit line BL is set so as to intersect with the word line WL and connected with the magnetic tunnel junction portion MTJ.
Data is written in the MTJ memory cell MCDD by supplying a data-write current to the word line WL and bit line BL. The direction of the data-write current is set in accordance with the level of write data similarly to the case of a memory using an access transistor.
A word line WL corresponding to a selected memory cell is set to a low-voltage (e.g. ground voltage Vss) state when data is read. In this case, by precharging a bit line BL to a high-voltage (e.g. power-supply voltage Vcc) state, it is possible to supply a sense current Is to the magnetic tunnel junction portion MTJ because the access diode DM is turned on. However, because a word line WL corresponding to an unselected memory cell is set to a high-voltage state, a corresponding access diode DM is kept turned off and the sense current Is does not circulate.
Thus, also in the case of an MJT memory cell using an access diode, it is possible to execute data read and data write.
FIG. 49 is a structural drawing when setting the MTJ memory cell shown in FIG. 48 on a semiconductor substrate.
Referring to FIG. 49, an access diode DM is formed with an N-type region NWL on a main semiconductor substrate SUB and a P-type region PAR formed on the N-type region NWL. FIG. 49 shows an N well as a case of forming an N-type region.
The N-type region NWL corresponding to the cathode of an access diode DM is connected with a word line WL set to a metallic wiring layer M1. The P-type region PAR corresponding to the anode of the access diode DM is electrically connected with a magnetic tunnel junction portion MTJ through a barrier metal 140 and a metallic film 150. A bit line BL is set to a metallic-wiring layer M2 and connected with the magnetic tunnel junction portion MTJ. Thus, by using an access diode instead of an access transistor, it is possible to constitute an MTJ memory cell advantageous for high integration.
However, because a data-write current circulates through the word line WL and bit line BL under data write, a voltage drop due to the data-write current occurs in these wirings, respectively. Because the voltage drop occurs, the PN junction of the access diode DM may be turned on at a part of the MTJ memory cell in which data will not be written depending on a voltage distribution on the word line WL and bit line BL. As a result, erroneous data write may be executed because an unexpected current circulates through the MTJ memory cell.
Thus, a conventional MTJ memory cell MCDD using an access diode is advantageous for high integration but it has a problem that the data write operation becomes unstable.
The present invention is made to solve the above problem and its object is to accelerate and stabilize the data read operation of an MRAM device having an MTJ memory cell.